CAPSL Probabilistic Spin Logic for Low-Energy Boolean and Non-Boolean Computing

CAPSL-T4: Architectures and Systems from Probabilistic Spin Circuits to Benchmarking

In this theme, the team will design, simulate, and benchmark PSL Cores consisting of high kBT p-transistor weights and low kBT p-transistor probabilistic input/output units. Additionally, the maximum and optimal PSL Core sizes for implementing interconnected networks of PSL Cores to realize Deep Belief Networks of hierarchically organized RBMs for deep learning applications will be researched. P-transistor models will be used for the initial designs and we will develop a self-contained SPICE model with predictive transistor models (e.g. 10nm or 7nm) incorporating necessary LLG equations for processional motion of a time-varying magnetization vector.