p-bit based Classification Architecture Recognized at ACM GLSVLSI Conference

May 29, 2018

In this work, the CAPSL team’s device-level simulations based on precise physics relations were used to validate the sigmoidal relation between the output probability of a p-bit and its input currents. Characteristics of the resistive networks and p-bits were modeled in SPICE to perform a circuit-level simulation investigating the performance, area, and power consumption tradeoffs of the weighted array crossbar architecture. These results were used to design PSL-based Restricted Boltzmann Machines (RBMs) using Contrastive Divergence learning strategies on classification tasks such as image recognition. Multiple RBMs were organized hierarchically to realize Deep Belief Networks (DBNs) for energy-efficient machine learning capabilities with PSL devices. The DBN topologies were assessed for energy, accuracy, and throughput using MNIST database handwritten digit recognition problems. Area and energy reductions on the order of 100x and 1000x, respectively, were demonstrated over recent CMOS-only approaches, while achieving 96.3% recognition accuracy using a 784x800x800x10 DBN trained by 5,000 input samples.