Project SCALE SoC: SoC design, verification, programming, and test Program Engineering First Time Researcher (FTR) Fellowship Term Spring 2026 Status Closed Research Area System on Chip Design, Integrated Circuit Testing, Embedded Systems Description This project is restricted to Purdue SCALE Students. Please go to the SCALE FTR Page in the SCALE group on nanoHUB to read the full project description and requirements: https://nanohub.org/groups/scale/research/purdue/ftr All questions about this project should go to the faculty and mentor listed on the project description. Abbreviated description: System on Chip Extension Technologies (SoCET) is a long-running chip design team intended primarily for undergraduates to get experience in as many aspects of chip design, fabrication, and test as possible. Work on SoCET directly supports the SCALE program for which System on Chip design is one of the five specialty areas specifically targeted by SCALE. The team is organized like a small chip design company with sub-teams for logic design, verification, chip-layout, analog design, printed circuit board (PCB) design, test, software, and special research projects in collaboration with research groups in ECE. Special projects include AI hardware accelerator design, GPU architecture, hardware security, and signal processing for space applications. Some project areas have very specific prerequisite requirements, so team leaders will work with you to evaluate your background and interests and assign you to an appropriate sub-team or special project. Almost any kind of background in circuit design, logic design, circuit simulation, computer architecture, and microcontroller programming will be useful in some but not all parts of the team. For more details on possible projects and sub-teams, see https://engineering.purdue.edu/SoC-Team. Supervisor Mark C Johnson Mentor Cole Aaron Nelson Type of work required The expected contributions will depend on the area of the SoCET to which you are assigned. Depending on your background, part of the work will involve learning skills necessary for the assignment project. Possible contributions include creation of subsystems to be used in a future chip design, creation of circuit layouts for an IC design, writing software to be used on an existing System on Chip design, FPGA prototyping, design of printed circuit boards, for IC testing, or participation in research collaborations with other faculty. See https://engineering.purdue.edu/SoC-Team for more examples.

Websites https://engineering.purdue.edu/SoC-Team
https://nanohub.org/groups/scale/research/purdue/ftr Qualifications 1. You must be a SCALE student to be considered for this project. SCALE Students: Please check that your IDP and other information (resume, Linked In, Career Goals, etc.) in the SCALE Web App is up-to-date. If you are not yet a SCALE student, you can concurrently apply to SCALE and to this FTR project. Read more about SCALE and access the SCALE application link here: https://www.scale4me.org/students. 2. Preferred Majors: • Selected participants will usually be taken from electrical engineering, computer engineering, or computer science, but other majors will be considered if one has skills or experience directly relevant to chip design and testing. 3. Academic Years Eligible: • All Academic Years 4. Required Experience and Skills: • None except strong motivation and problem-solving ability. 5. Desired Experience and Skills: • Digital design and simulation using Verilog • Analog circuit design • Printed circuit board design • Computer processor design • IC testing • Microcontroller programming. Credit Hours 0 Weekly Hours 10 (estimated)