sealPurdue News

August 1999

Engineers way to faster, less-costly computer chips

WEST LAFAYETTE, Ind. -- Engineers at Purdue University have developed a method to make smaller, faster computer chips by stacking electronic devices -- such as transistors 50 times smaller than a human blood cell -- in a virtually unlimited number of layers, as opposed to conventional single-layer designs.

The vertically connected layers may increase the speed and the number of transistors in a computer chip.

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Present technology forms electronic devices by sculpting silicon in numerous steps; instead of sculpting, the Purdue method "grows" desired features from scratch.

The researchers have invented a method called epitaxial lateral overgrowth, in which silicon is grown into distinct "islands" that extend vertically, linking up with the next layer. The result is multiple layers of transistors with extremely short connections, and hence, faster and denser circuits, says Gerold Neudeck, a professor of electrical and computer engineering who co-wrote a paper about the work that appeared in June in a scientific journal.

Faster circuits lead to computers with higher performance. Denser circuits help decrease the cost of chips by increasing the number that can be manufactured in a given area.

To grow the silicon into precisely placed islands, Neudeck first etches holes into silicon dioxide with hydrofluoric acid and then fills the holes with silicon by using a well-known process called chemical vapor deposition.

"It's sort of like pouring concrete into a form," Neudeck says.

The resulting "seeds" of silicon can then be extended, using epitaxial lateral overgrowth, into the silicon islands needed to build electronic devices in vertical layers.

Such precise structuring is not possible with conventional technology, in which silicon is deposited as a blanket onto the surface of a wafer and then formed into islands during numerous steps such as chemical etching.

The Purdue method builds the islands automatically, skipping about 10 of the first 32 steps now required to make conventional chips. A major potential benefit of the technology is that there is theoretically no limit to the number of layers that could be stacked, offering the possibility of making more complex circuits in less space, thus increasing the performance of computer chips.

Purdue engineers have used the method to make a new type of transistor -- called a double-gate transistor -- which carries twice the current and could work more than twice as fast as conventional devices. The method might be used to make transistors 150 nanometers wide. By comparison, transistors commonly used in today's integrated circuits are roughly 3,000 by 5,000 nanometers, and a human red blood cell is about 7,500 nanometers.

The patented process allows the two halves of microelectronic switches, which are essential components in the processing of computer data, to be connected vertically instead of horizontally, bringing them hundreds of times closer than would be possible otherwise. Because the devices are closer to each other, the circuit performs faster.

The findings are detailed in a paper appearing in the May/June issue of the Journal of Vacuum Science and Technology B; Microelectronics and Nanometer Structures, published by the American Institute of Physics. The paper was written by Neudeck, graduate research assistants Sangwoo Pae and Tai-chi Su, and research engineer John P. Denton, all from the Purdue School of Electrical and Computer Engineering.

The work has been funded by the Semiconductor Research Corp., which is an industry-government consortium, and the Defense Advanced Research Projects Agency.

Source: Gerold Neudeck, (765) 494-3513;

Writer: Emil Venere, (765) 494-4709;

Purdue News Service: (765) 494-2096;

NOTE TO JOURNALISTS: Copies of the journal article mentioned in this story are available from Emil Venere at Purdue News Service, (765) 494-4709,


This drawing depicts a new way of making computer chips in layers. It shows four "islands" made with epitaxial lateral overgrowth, or ELO, connecting vertical layers of electronic devices made with a technology called silicon on insulator, or SOI.
Color photo, electronic transmission, and Web and ftp download available. Photo ID: Neudeck.chips

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Multiple layers of silicon-on-insulator for nanostructure devices
Gerold W. Neudeck, Sangwoo Pae, John P. Denton, and Tai-chi Su

A new method for silicon-on-insulator (SOI) is presented that has very few stacking defects and produced multiple layers of single crystal silicon surrounded by thermal SiO2. The technique requires selective epitaxial growth, epitaxial lateral overgrowth, and chemical mechanical planarization to form SOI islands stacked in multiple layers. Islands of silicon as small as 150 X 150 X 40 nm were fabricated. Larger SOI islands in two SOI layers, with grown vertical interconnections between layers, were 5 X 500 X 0.1 m m. Only one stacking fault was observed in 85,000 m m2 of the first layers and none in the second layers. P-channel metal-oxide-semiconductor field effect transistors with gate lengths of less than j~ 100 nm were fabricated in the thin SOI islands. They had normal current-voltage plot characteristics with less than 0.2 pA/m m of leakage current, illustrating the quality of the material in both SOI layers and at the silicon to thermal-oxide interfaces. The devices had measured sub threshold slopes of 76 mV/decade and good saturated current drives.

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