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September 17 @ 10:00 AM - 11:00 AM - BRK 1001
ABSTRACT: The “ideal” normally-off operated GaN MISFET device structure and fabrication method are demonstrated. The gate is inherently self-aligned to the source/drain. The source/drain with low parasitic resistance were formed using Si ion implantation through thin a SiNx layer. Both maximum drain current of 310 mA/mm and transconductance of 40 mS/mm were obtained. GaN p-n junction diodes on free-standing GaN substrates with low dislocation density around 106/cm2 were also demonstrated. Reduction of the leakage current below 10-6A/cm2 and high breakdown voltage up to 1100 V using the field plate structure were obtained.
BIO: Kazuki Nomoto received the MS and PhD degrees in electrical engineering from Hosei University, Tokyo, Japan, in 2006 and 2009, respectively. Since 2009, he joined Research Center for Micro-Nano Technology, Hosei University, Japan. He has been working in the area of GaN devices as a postdoctoral fellow. His current research is 1) Investigation of high power and high temperature operation p-n junction diodes and n-p-n bipolar junction transistors on free-standing GaN substrates and 2) Ion-Implanted GaN HEMTs and MISFETs.
Host: Professor James A. Cooper, firstname.lastname@example.org
December 13 @ 7:30 AM - 4:30 PM IUPUI Campus in Purdue University Campus in the Campus Center (CE), room 409.
February 3 @ 7:45 AM - 2:30 PM PMU South Ballroom on the Purdue University West Lafayette Campus
Office of the Vice President for Research
610 Purdue Mall
West Lafayette, IN 47907-2040