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July 25 @ 10:00 AM - 11:00 AM - BRK 1001
Exploiting unconventional physical properties, several nanodevices showed an alternative to Moore’s Law by the increase of their functionality rather than the pure scaling. Innovative device behaviors transduce to new circuit/architecture opportunities. In the field of nanoelectronics, a technology-design co-integration approach is necessary. Such approach simultaneously covers the design of the technology and the application circuits, in order to jointly adapt them to the targeted application. To support this statement, we comment on the opportunities brought at the circuit and architecture levels by resistive memory technology and controllable-polarity transistors.
In the first part of the talk, we assess the use of Resistive memories (ReRAMs) in other applications than high-density storage arrays. ReRAMs are promising candidates to replace traditional non-volatile memories, thanks to their better footprint scalability, faster programming time and enhanced endurance. First, we combine their properties with CMOS to build low-power non-volatile flip-flop circuits that open new opportunities for many energy efficient computing systems. Then, we move away from the pure storage application by deriving their use to digital reconfigurable logic circuits. In particular, we propose to leverage the intrinsic physical properties of ReRAMs to radically improve the different functional blocks of FPGAs. Indeed, instead of only using the ReRAMs as a memory, we extend their use as non-volatile switches and we design innovative circuits for routing elements. The outcome of such an approach is a complete redesign of the FPGA internal structure in which the memory/data path logic will be merged, in order for the memories to take integral part in the data path. This approach is expected to lead to a breakthrough in the field of high-performance reconfigurable platforms demonstrating more density, higher performance and higher energy efficiency.
In the second part of the talk, we move to a novel class of computation devices, that exhibit a controllable-polarity property. At advanced technology nodes, Schottky contacts at the channel interfaces are becoming challenging to avoid. Hence, devices face an ambipolar behavior, i.e., that devices exhibit n- and p-type characteristics simultaneously. We will see that such a property can be efficiently leveraged for logic computation. Indeed, we recently demonstrated that by constructing independent double-gate structures on vertically-stacked NanoWires FETs (NWFETs), the device polarity can be electrostatically forced to be either nor p-type. Controllable-polarity devices are logical bi-conditional on both gate values and enable a compact realization of XOR/MAJ-based logic functions, which are not implementable in CMOS in a compact form. Hyper regular architectures and new EDA challenges, supporting the higher expressive power brought by this technology, are discuss to show the broad research horizons offered by controllable-polarity devices.
Bio: Pierre-Emmanuel Gaillardon works for EPFL, Lausanne, Switzerland, as a research associate at the Laboratory of Integrated Systems (LSI). He holds an Electrical Engineer degree (CPE-Lyon, France, 2008), a M.Sc. degree (INSA Lyon, France, 2008) and a Ph.D. in Electrical Engineering (University of Lyon, France, 2011). Previously, he was research assistant at CEA-LETI. He is recipient of the Cinnov 2011 best thesis award and the Nanoarch 2012 best paper award. He has been serving as TPC member for CMOSETR'13-15, Nanoarch'12-14, ISVLSI'14 conferences and is reviewer for several journals (AIP APL, IEEE TNANO, IEEE TVLSI, ACM JETC), conferences (ICECS, ISCAS) and funding agencies (ANR, Chairs of Excellence program of Nanosciences Foundation). The research activities and interests of Dr. Gaillardon are currently focused on emerging nanoscale devices and their use in digital circuits and architectures.
December 2 @ 2:00 PM - 3:00 PM WANG 1004
December 3 @ 4:00 PM - 7:00 PM Room PFEN 120 - then on to 9 Irish Brothers at 5:00pm
December 8 @ 4:00 PM - 5:00 PM Birck 1001
Office of the Executive Vice President for Research and Partnerships
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