Scaling of transistors – also known as miniaturization - has been the driving force behind the improvement of chip performance over the last few decades. This trend is intimately connected with the claim to maintain a tight electrostatic gate control. The argument is as follows: Shrinking the device length is a means to improve the switching speed of field-effect transistors. The reduction of transistor length however has to be accompanied by the reduction of other device dimensions as well in order to maintain proper transistor behavior. Historically, the gate oxide thickness has been scaled together with the gate length to avoid a loss of electrostatic gate control. With gate oxide thicknesses approaching 1nm, gate leakage becomes an important constrain.
Figure 1: Schematics of the dual-gate silicon nanowires field-effect
transistor with silicided contacts.
While alternative approaches as the use of high-k dielectrics offer a chance to further extend the scaling of the gate dielectric, there is also another knob that has been hardly utilized in the past. The so-called body thickness – the thickness of the channel – if made small enough can support the desired scaling of the gate length. In other words, if the body thickness is made small, the channel length can be reduced without the loss of electrostatic gate control and without the introduction of “leaky” gate oxides. This improves the device performance and extends the possibility of scaling transistors.
One material that naturally offers an extremely thin body is a carbon nanotube. Another prominent candidate is a nanowire. Because of the advantages silicon nanowires offer when it comes to the integration with existing silicon CMOS processes, exploring this material class is an important task at hand. Interestingly, even though silicon is probably the best studied material, our knowledge about transport in silicon nanowires is rather limited. Moreover, concepts that are well established for bulk-type (that includes here also conventional MOSFETs) do not apply in the same way to one-dimensional or quasi one-dimensional structures as nanowires.
Figure 2: Scanning electron micrograph of a silicon nanowire
between two nickel contacts with silicided source/drain extensions.
A study that illustrates this aspect very clearly is discussed here. A silicon nanowire transistor as shown in the schematic of figure 1 had been fabricated. In the majority of silicon nanowire device studies metal contacts are immediately attached to the nanowires and act as source and drain contacts. However, here we created an intermediate metal silicide layer that connects the intrinsic nanowire portion with the metal electrodes [1]. The advantage of such a structure is a reduced contact resistance that translates into improved device performance.
Figure 3: Subthreshold and output characteristics of a dual-gate
silicon nanowires field-effect transistor with silicided contacts.
When applying conventional silicide recipes though, it became quickly apparent that the formation of nickel silicide occurred at substantially lower temperatures and caused much longer source/drain extensions than in conventional silicon structures. We were able to quantitatively describe this effect and develop nanowire specific recipes that allow implementing our findings into future silicon nanowire FETs. Figure 2 shows an image of a silicon nanowire between two nickel electrodes after the formation of nickel silicide. The bright areas extending from the metal electrodes into the wire area are clearly visible. After finalizing device fabrication by the deposition of a top-gate as shown in figure 1, electrical device characteristics were obtained. Figure 3 shows a set of subthreshold as well as output characteristics form these types of devices. While at a first glance rather conventional electrical characteristics are obtained, a detailed analysis of the data reveals important insights into the critical contact formation in the case of ultrathin body devices. In particular features like the non-ideal current dependence on the drain voltage for the most negative gate voltage – upper curve in the output characteristics shown in figure 3 – can be used to obtain information about the energetic line-up between the Fermi level in the metal electrodes and the conduction/valence band structure of the semiconducting nanowire.
References
[1] J. Appenzeller, J. Knoch, E. Tutuc, M. Reuter, and S. Guha, IEDM Technical Digest, 555 (2006).
