One of the – if not THE – most pressing challenge/s is the ever increasing amount of total power consumed by state-of-the-art high performance chips. While scaling has been the key to improved device and corresponding circuit performance, not all transistor parameters have been scaled as originally suggested. In particular supply voltages have remained at a rather high constant level of around 1V since a number of chip generations. This fact has serious implications. With the number of devices per chip steadily increasing the total dissipated power has increased to a point where cooling has become a serious issue to prevent chip failure. The task at hand is to reduce the supply voltage without sacrificing on-state performance and switching speed.
Figure 1: Electron micrograph of the first tunneling carbon
nanotube field-effect transistor. The above schematic shows
the arrangement of contacts and gates.
Over the last 10 years carbon nanotubes (CNs) have attracted an increasing interest as building blocks for nano-electronics applications. Due to their unique properties enabling e.g. ballistic transport at room-temperature over several hundred nanometers [1,2], high performance CN field-effect transistors (FETs) have become feasible. The successful improvement of CNFET performance however is not merely a result of the application of established concepts. It is indeed a consequence of the detailed study of the material specific properties that have guided the research on CN-based transistor applications. An example of this is the critical observation that CNFETs in fact behave as Schottky barrier devices with barrier thicknesses much smaller than commonly observed in bulk-type structures. It was found that switching in nanometer size semiconductors, such as carbon nanotubes, contacted with source/drain metal electrodes is determined entirely by the metal/semiconductor interfaces and their field-dependence [3,4]. Making use of this particular type of nanotube property, we have been able to relate the performance of nanotube devices with their diameters [5].
More importantly, this particular aspect – the ultrathin achievable tunneling barrier - has turned out to be the key ingredient for the successful implementation of the so-called tunneling carbon nanotube field-effect transistor T-CNFET [6]. This device shows a much more abrupt switching behavior than can be obtained with any conventional transistor approach, evidence that nano-materials can be used to create drastically different and more efficient switches in principal. The device discussed in reference [6] is displayed in figure 1.
Figure 2: Band bending situation in the on-state of
(a) a p/i/p T-CNFET and (b) an n/i/p T-CNFET.
(a) has been realized with the device displayed in fig. 1.
An Al-gate under the carbon nanotube middle-region together with the silicon substrate gate enable a band profile as illustrated in figure 2a). Holes injected from the source into the nanotube channel can tunnel into the gated region (gray) of the transistor if high enough positive voltages are applied – they are leaving the valence band close to the drain and tunnel into the conduction band. For negative drain voltages, those carriers can leave the device on the drain side through the valence band resulting in a band-to-band tunneling current. This unusual type of switch offers a unique opportunity to address the power consumption aspect mentioned above. It is indeed possible to change the current by orders of magnitude with a rather small supply voltage when the bands in the “gray area” of figure 2a) are moved relative to the two “white areas”. In fact the change in current per applied voltage is larger than can ever be achieved with a conventional device concept (for details see [6] and [9]).
The successful experimental realization of the first T-CNFET is illustrated in figure 3. Two different devices (red and orange data points) both show the anticipated abrupt switching behavior at room-temperature. While a conventional field-effect transistor needs at least 60mV to change the current through the device by one order of magnitude, this first demonstration achieves the same with just 40mV – a critical prove of principal that the proposed tunneling device concept is viable.
Figure 3: Electrical characteristics of the first set of
T-CNFETs. Two measurements (red and orange) are shown,
both indicating the anticipated abrupt switching behavior.
It should be noted that the device current for positive gate voltages is still too small to be sufficient for actual circuit applications. This is the case since these first devices were fabricated with a non-ideal gate configuration for simplicity. Future generations of T-CNFETs will explore more
sophisticated gate and doping arrangements resulting in a band bending situation as displayed in figure 2b). The advantage of such a structure is that only one tunneling event is involved, allowing for a higher on-state performance.
Last, it is worth mentioning that we are also exploring the possibility to include nano-devices into simple circuit applications. The latest accomplishment [7] in this context is to combine carbon nanotube transistors in a CMOS-type 5-stage ring oscillator [8], an important demonstration that elevates nanotube applications from the devices level to the circuit level and allows for the more detailed study of their high frequency properties. The main breakthrough in this circuit related work is the successful tuning of the threshold voltage of n-type CNFETs and p-type CNFETs by means of properly chosen gate metals and gate dielectrics.
References
[1] S. Wind, J. Appenzeller, and Ph. Avouris, Phys. Rev. Lett. 91, 058301 (2003).
[2] A. Javey, J. Guo, Q. Wang, M. Lundstrom, and H. Dai, Nature 424, 654 (2003).
[3] S. Heinze, J. Tersoff, R. Martel, V. Derycke, J. Appenzeller, and Ph. Avouris, Phys. Rev. Lett. 89, 106801 (2002).
[4] J. Appenzeller, J. Knoch, V. Derycke, R. Martel, S. Wind, and Ph. Avouris, Phys. Rev. Lett. 89, 126801 (2002).
[5] Z. Chen, J. Appenzeller, J. Knoch, Y.-M. Lin, and Ph. Avouris, Nano Letters 5, 1497 (2005).
[6] J. Appenzeller, Y.-M. Lin, J. Knoch, and Ph. Avouris, Phys. Rev. Lett. 93, 196805 (2004).
[7] Note that this work has been performed at IBM T.J. Watson Research Center, Yorktown Heights, NY with Dr. Z. Chen as the main PI.
[8] Z. Chen, J. Appenzeller, Y.-M. Lin, J.S. Oakley, A.G. Rinzler, J. Tang, S. Wind, P. Solomon, and Ph. Avouris, Science 311, 1735 (2006).
[9] J. Appenzeller , Y.-M. Lin, J. Knoch, and Ph. Avouris, IEEE Transactions on Electron Devices 52, 2568 (2005).
